IMC 2026Live demo · 02 of 02
Entra × IIT Dharwad

Seven modes, one tyre

A tyre sensor lives for years on a coin cell, so it spends most of its life asleep. The System Controller Unit decides when the RISC-V core may run, when it must sleep, and when heat forces an alarm. Wake it up and try to break it.

Car fitted with TPMS sensors, linked to the dashboard over 433 MHz with a 125 kHz wake-up

Inside the system

tyre → sensor module → ECU → dashboard
Tyre VALVE-STEM SENSOR MODULE TPMS SoC RISC-V 3.39 MHz C38 P/T LF 125 kHz 3 V COIN CELL 433 MHz data 125 kHz wake TPMS ECU IDLE no frames yet In the vehicle CAN TPMS --.- psi WAITING Dashboard

SCU mode state machine

scu_controller · SCU_CSR[23:20]
fresh ON (re-armed) frame ready timer 100 ms OFF watchdog over-temperature on a fresh ADC sample alert burst sent · terminal
  • Firmware mode
  • Wake
  • Sleep, clock gated
  • Thermal trip
  • Radio data
  • OK, CPU running

Solid arrows are the normal cycle. Over-temperature can trip from any active mode, and OFF or the mode watchdog can send any active mode to Deep Sleep; one arrow stands for each.

Now in
Deep Sleep
Owner
CPU clock
Wake armed
Silicon time
0.000 s

Drive the chip

ON line: LF 125 kHz
12-bit ADC code. Trip threshold 0xFE0 (programmable). Checked only when a fresh sample is taken.
TDK C38 gauge, 0–10 bar onto the 12-bit ADC.

RF frame · 433 MHz ASK

128 bits · 20 kbps · 6.42 ms

Cycle budget

of each cycle the CPU clock is running

Event log

silicon time